Scheduling tasks using targeted pipelines
US12020067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | May 17, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of scheduling instructions within a parallel processing unit is described. The method comprises decoding, in an instruction decoder, an instruction in a scheduled task in an active state, and checking, by an instruction controller, if an ALU targeted by the decoded instruction is a primary instruction pipeline. If the targeted ALU is a primary instruction pipeline, a list associated with the primary instruction pipeline is checked to determine whether the scheduled task is already included in the list. If the scheduled task is already included in the list, the decoded instruction is sent to the primary instruction pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.