Discharge circuits for erasing NAND flash memory
US12020752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Sep 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for discharging a memory device after an erase operation. The method comprises grounding a source line of the memory device; and switching on a discharge transistor to connect a bit line of the memory device to the source line by maintaining a constant voltage difference between a gate terminal of the discharge transistor and the source line. The method also includes comparing an electrical potential of the source line with a first predetermined value; and floating the gate terminal of the discharge transistor when the electrical potential of the source line is lower than the first predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.