ATPG testing method for latch based memories, for area reduction
US12020760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Dec 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.