Patent · US Active

Memory circuit architecture with multiplexing between memory banks

US12020766B2 · kind B2 · utility

0Cited by

5References

15Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Pradeep Raj · Atrauli, IN
Rahul Sahu · Kanchinakote, IN
Sharad Gupta · New Delhi, IN
Hemant Patel · Hsinchu, TW
Diwakar SINGH · Kanchinakote, IN

Key dates

Filing date	Mar 10, 2022
Grant date	Jun 25, 2024
Priority date	—
Expiry date	Mar 10, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.