Test structure and testing method thereof
US12020993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2021 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Dec 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes: providing a substrate defining a scribe line region and a device region adjacent to the scribe line region; depositing a first mask layer over the device region and the scribe line region; patterning the first mask layer to define a plurality of first areas in the device region and a plurality of second areas in the scribe line region, wherein the first areas and the second areas are parallel and extending in a first direction from a top-view perspective; performing a first ion implantation to form first well regions in the first areas and second well regions in the second areas; coupling conductive pads to the second well regions; and performing a test on the second well regions through the conductive pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.