Warpage control of semiconductor die
US12021002B2 · kind B2 · utility
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5References
20Claims
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Key dates
| Filing date | Aug 9, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Aug 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a metal structure in the dielectric layer, a first metal pad over the metal structure, a first oxide-based passivation layer over the first metal pad, a second oxide-based passivation layer over the first oxide-based passivation layer, and a bump electrically connected to the first metal pad. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.