Semiconductor package and method of manufacturing the semiconductor package
US12021034B2 · kind B2 · utility
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31References
20Claims
0Family size
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Key dates
| Filing date | Mar 11, 2021 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Aug 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.