Semiconductor package including interposer and method of manufacturing the semiconductor package
US12021036B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Nov 14, 2022 |
| Grant date | Jun 25, 2024 |
| Priority date | — |
| Expiry date | Nov 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.