Method of forming top select gate trenches

US12021126B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Hang Yin · Beijing, CN
• Zhipeng Wu · 红钢城街道, CN
• Kai Han · Zhubeikou, TW
• Lu Zhang · Shanghai, CN
• Pan Wang · Shanghai, CN
• Xiangning Wang · 红钢城街道, CN
• Hui Zhang · Renqiu City, CN
• Jingjing Geng · 红钢城街道, CN
• Meng Xiao · 红钢城街道, CN

Key dates

• Filing date: Dec 23, 2020
• Grant date: Jun 25, 2024
• Expiry date: Nov 28, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.