Differential unit element for multiply-accumulate operations on a shared charge transfer bus
US12026479B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2021 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Jun 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to differential charge transfer lines through respective charge transfer capacitor Cu. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through a charge transfer capacitor Cu to charge transfer lines. Multiple Unit Elements may be placed in parallel to sum and scale the charges from the charge transfer lines, the charges coupled to an analog to digital converter which forms the dot product output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.