Semiconductor device with unbalanced die stackup
US12027497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2022 |
| Grant date | Jul 2, 2024 |
| Priority date | — |
| Expiry date | Nov 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1438
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.