Method of forming integrated assemblies having transistors configured for high-voltage applications

US12027621B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Zia A. Shafi · Boise, US
• Luca Laurin · Lissone, IT
• Durga P. Panda · Boise, US
• Sara Vigano' · Monza, IT

Key dates

• Filing date: Jul 19, 2022
• Grant date: Jul 2, 2024
• Expiry date: Jul 19, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856

Abstract

Some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. The first source/drain region is spaced from the channel region by an intervening region. The first and second source/drain regions are gatedly coupled to one another through the channel region. A second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. A lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. Some embodiments include methods of forming integrated assemblies.