Semiconductor device configured for gate dielectric monitoring
US12032014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2020 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Feb 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/281
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.