Calibration data generation circuit and associated method
US12032020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2022 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Dec 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.