Circuit and method for translation lookaside buffer (TLB) implementation
US12032488B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2022 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Jan 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and corresponding method provide a translation lookaside buffer (TLB) implementation. The circuit comprises a plurality of TLB banks and TLB logic. The TLB logic computes a plurality of hash values of a tag included in a memory request. The TLB logic locates, based on hash values of the plurality of hash values computed, a contiguous translation entry (TE) and a non-contiguous TE in different TLB banks of the plurality of TLB banks. The TLB logic determines a result by comparing the tag with the contiguous TE located and by comparing the tag with the non-contiguous TE located. The TLB logic outputs the result determined toward servicing the memory request. The TLB logic advantageously enables the TLB implementation to support contiguous pages using standard random-access memories for the plurality of TLB banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.