Synchronization in multi-chip systems
US12032511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2022 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Jun 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.