Semiconductor layout context around a point of interest
US12032892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2019 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Sep 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for analyzing a semiconductor layout design around a point of interest (POI) are disclosed. Semiconductor layout designs are a representation of an integrated circuit in terms of planar geometric shapes which make up the components of the integrated circuit, and are used to manufacture the integrated circuit. The layout design may be analyzed using one or more POI-based approaches to determine whether to modify the layout design. In one POI-based approach, set of kernels, tailored to the downstream application, are convolved with a representation of the layout design about or around the POI in order to generate a signature associated with the POI. In turn, the signatures may be analyzed based on the downstream application. Another POI-based approach consists of analyzing geometrical parameters associated with the POI, which may be used during a design stage to identify and modify problem areas in the layout design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.