David Abercrombie
23Patents
9h-index
26Co-inventors
75Inventor score
Filing activity: Aug 26, 1996 → Aug 30, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5666063A | Method and apparatus for testing an integrated circuit | Emerging Cross-Sectional Technologies | 111 | Expired |
| US6807655B1 | Adaptive off tester screening method based on intrinsic die parametric measurements | Electricity | 87 | Expired |
| US5937324A | Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits | Electricity | 62 | Expired |
| US5798568A | Semiconductor component with multi-level interconnect system and method of manufacture | Electricity | 38 | Expired |
| US7062415B2 | Parametric outlier detection | Physics | 14 | Expired |
| US7454387B2 | Method of isolating sources of variance in parametric data | Physics | 11 | Active |
| US8612919B2 | Model-based design verification | Physics | 9 | Active |
| US7460211B2 | Apparatus for wafer patterning to reduce edge exclusion zone | Emerging Cross-Sectional Technologies | 9 | Active |
| US6980917B2 | Optimization of die yield in a silicon wafer “sweet spot” | Physics | 9 | Expired |
| US7039556B2 | Substrate profile analysis | Emerging Cross-Sectional Technologies | 7 | Expired |
| US7725849B2 | Feature failure correlation | Emerging Cross-Sectional Technologies | 6 | Expired |
| US7174281B2 | Method for analyzing manufacturing data | Physics | 4 | Expired |
| US7390680B2 | Method to selectively identify reliability risk die based on characteristics of local regions on the wafer | Electricity | 1 | Expired |
| US6880140B2 | Method to selectively identify reliability risk die based on characteristics of local regions on the wafer | Electricity | 1 | Expired |
| US9652574B2 | Simultaneous multi-layer fill generation | Emerging Cross-Sectional Technologies | 1 | Active |
| US7137098B2 | Pattern component analysis and manipulation | Electricity | 1 | Expired |
| US7930655B2 | Yield profile manipulator | Physics | 0 | Active |
| US7395522B2 | Yield profile manipulator | Physics | 0 | Active |
| US12032892B2 | Semiconductor layout context around a point of interest | Physics | 0 | Active |
| US7653523B2 | Method for calculating high-resolution wafer parameter profiles | Electricity | 0 | Expired |
| US6658361B1 | Heaviest only fail potential | Electricity | 0 | Expired |
| US9507902B2 | Simultaneous multi-layer fill generation | General | 0 | Revoked |
| US10552565B2 | Simultaneous multi-layer fill generation | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.