Memory circuit comprising a plurality of 1T1R memory cells
US12033696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2022 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Dec 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a plurality of memory cells, each memory cell including a resistive memory element and a selection transistor of the FDSOI type connected in series with the resistive memory element. The selection transistor includes a channel region, a buried insulating layer, a back gate separated from the channel region by the buried insulating layer. The memory circuit further includes a circuit for biasing the back gate of the selection transistors, the biasing circuit being configured to apply a forward back-bias to the selection transistor of at least one memory cell during a programming or initialisation operation of the at least one memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.