Semiconductor device and method
US12033940B2 · kind B2 · utility
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15References
20Claims
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Assignee
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Key dates
| Filing date | Nov 17, 2020 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Dec 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.