Contact pads of three-dimensional memory device and fabrication method thereof
US12033966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2021 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Jul 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes preparing a stacked device having a first array device and a second array device, forming an opening on a back side of the second array device, and forming one or more contact pads in the opening. The first array device includes first front pads on a face side of the first array device and first back pads on a back side of the first array device. The second array device includes second front pads on a face side of the second array device and bonded with the first back pads. The one or more contact pads are disposed at a level proximate to the second front pads with respect to the first array device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.