Active matrix substrate
US12034010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2023 |
| Grant date | Jul 9, 2024 |
| Priority date | — |
| Expiry date | Mar 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
Abstract
An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.