Patent · US Active

Multi-transistor stack bitcell architecture

US12035517B2 · kind B2 · utility

0Cited by

0References

17Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Amit Chhabra · Noida, IN
David Victor Pietromonaco · San Jose, US

Key dates

Filing date	Dec 17, 2020
Grant date	Jul 9, 2024
Priority date	—
Expiry date	May 30, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH10D88/01
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.