Hardware software communication channel to support direct programming interface methods on FPGA-based prototype platforms

US12038819B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Renu Patle · Folsom, US
• Hanmanthrao Patli · Folsom, US
• Rakesh Mehta · Tampa, US
• Hagay Spector · Sderot, IL
• Ivan Herrera Mejia · Park Village, US
• Fylur Rahman Sathakathulla · Folsom, US
• Gowtham Raj Karnam · Folsom, US
• Mohsin Ali · San Jose, US
• Sahar Sharabi · Beer Yaakov, IL
• Abraham Halevi Fraenkel · Jerusalem, IL
• Eyal Pniel · Beer Sheva, IL
• Ehud Cohn · Ora, IL
• Raghav Ramesh Lakshmi · Folsom, US
• Altug Koker · Cameron Park, US

Key dates

• Filing date: Jun 14, 2022
• Grant date: Jul 16, 2024
• Expiry date: Jun 14, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/3656
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.