Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

US12039001B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Subramaniam Maiyuran · Citrus, US
• Jorge Parra · Cameron Park, US
• Supratim Pal · Bengaluru, IN
• Ashutosh Garg · Sunnyvale, US
• Shubra Marwaha · Folsom, US
• Chandra Gurram · Folsom, US
• Darin Starkey · Roseville, US
• Durgesh Borkar · Folsom, US
• Varghese George · Folsom, US

Key dates

• Filing date: Apr 17, 2023
• Grant date: Jul 16, 2024
• Expiry date: Apr 17, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/08
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.