Static random access memory supporting a single clock cycle read-modify-write operation
US12040013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2022 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Jan 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.