Multi-transistor stack architecture in a single vertical stack
US12040232B2 · kind B2 · utility
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Key dates
| Filing date | Nov 3, 2022 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Nov 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
Abstract
Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.