Chip-scale package architectures containing a die back side metal and a solder thermal interface material
US12040246B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | Nov 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.