Connector for implementing multi-faceted interconnection
US12040272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2023 |
| Grant date | Jul 16, 2024 |
| Priority date | — |
| Expiry date | May 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.