Scan chain designing and circuit testing method
US12044721B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2022 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Mar 29, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2834
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan chain designing method includes: obtaining test points according to a gate-level netlist; determining integers M and N, wherein M and N are no greater than an amount X of the test points; selecting M and N test points to be a first and second set test points according to a priority; obtaining a first test coverage and a first test pattern count according to the first set test points and obtaining a second test coverage and a second test pattern count according to the second set test points; obtaining a predicted test coverage curve according to the first and second test coverages; determining an optimum amount O according to the predicted test coverage curve, the first and second test pattern counts, wherein O is no greater than X; and selecting O test points to arrange a scan chain according to the priority and the optimum amount O.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.