In-memory computing architecture and methods for performing MAC operations
US12045714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2023 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Feb 17, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operation of a semiconductor device that includes the steps of coupling each of a plurality of digital inputs to a corresponding row of non-volatile memory (NVM) cells that stores an individual weight, initiating a read operation based on a digital value of a first bit of the plurality of digital inputs, accumulating along a first bit-line coupling a first array column weighted bit-line current, in which the weighted bit-line current corresponds to a product of the individual weight stored therein and the digital value of the first bit, and converting and scaling, an accumulated weighted bit-line current of the first column, into a scaled charge of the first bit in relation to a significance of the first bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.