Patent · US Active

Automated root cause analysis for defect detection during fabrication processes of semiconductor structures

US12045969B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

Carl Zeiss SMT GmbH · DE

Inventors

Jens Timo Neumann · Shanghai, CN
Eugen Foca · Lauchheim, DE
Ramani Pichumani · Palo Alto, US
Abhilash Srikantha · Neu-Ulm, DE
Christian Wojek · Aalen, DE
Thomas Korb · Schwäbisch Gmünd, DE
Joaquin Correa · Oakland, US

Key dates

Filing date	Sep 28, 2020
Grant date	Jul 23, 2024
Priority date	—
Expiry date	Jan 24, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06T2207/30148
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method includes obtaining at least one 2-D image dataset of semiconductor structures formed on a wafer including one or more defects during a wafer run of a wafer using a predefined fabrication process. The method also includes determining, based on at least one machine-learning algorithm trained on prior knowledge of the fabrication process and based on the at least one 2-D image dataset, one or more process deviations of the wafer run from the predefined fabrication process as a root cause of the one or more defects. A 3-D image dataset may be determined as a hidden variable.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.