Non-volatile memory with short prevention
US12046294B2 · kind B2 · utility
0Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2022 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Dec 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.