Interconnect structure having a barrier layer along the sidewall of self-aligned via structures
US12046551B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | Apr 17, 2023 |
| Grant date | Jul 23, 2024 |
| Priority date | — |
| Expiry date | Apr 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.