Stacked memory with interface providing offset interconnects

US12046577B2 · kind B2 · utility

Assignee

• Tahoe Research, Ltd. · IE

Inventors

• Pete D. Vogt · Boulder, US
• Andre Schaefer · Hersbruck, DE
• Warren R. Morrow · Vancouver, US
• John B. Halbert · Beaverton, US
• Jin-Sung Kim · Hwaseong-si, KR
• Kenneth D. Shoemaker · Los Altos Hills, US

Key dates

• Filing date: May 28, 2019
• Grant date: Jul 23, 2024
• Expiry date: May 28, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/48
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.