Patent · US Active

Vertical memory devices

US12048153B2 · kind B2 · utility

0Cited by
4References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 26, 2021
Grant dateJul 23, 2024
Priority date
Expiry dateNov 11, 2042

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B41/27

Abstract

Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.