Routing circuit for computer resource topology
US12050532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2023 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Apr 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A routing circuit for an integrated circuit configured to access a set of resources that are organized according to a topology with a plurality of dimensions. The routing receives a request for a particular resource of the set of resources that includes an address that includes first and second sets of bits, the topology having a first dimension with n routing options (where n is not a power of two) and a second dimension with m routing options. The routing circuit determines first and second routing selections for the first and second dimensions by performing respective modulo-n and div-n operations on values formed from the address that include the first and second set of bits. The routing circuit then activates one or more selection signals in accordance with the first and second routing selections that are usable to cause the particular resource to be selected in response to the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.