Instruction and logic for code prefetching
US12050915B2 · kind B2 · utility
0Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2020 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Nov 27, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a fetch circuit to fetch instructions, the instructions including a code prefetch instruction; a decode circuit to decode the code prefetch instruction and provide the decoded code prefetch instruction to a memory circuit, the memory circuit to execute the decoded code prefetch instruction to prefetch a first set of code blocks into a first cache and to prefetch a second set of code blocks into a second cache. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.