Automatic tracking for clock synchronization based on delay line adjustment
US12051481B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2022 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Dec 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes: receiving a data signal (DQ) and a clock signal (DQS); generating an indicator signal by: delaying the data signal (DQ) to generate a delayed data signal (DQ′); sampling the data signal (DQ) and the delayed data signal (DQ′) using an edge of the clock signal (DQS) to generate a first sampled value and a second sampled value; and generating the indicator signal based on the first sampled value and the second sampled value; and adjusting one or more of a DQ adjustable delay line associated with the data signal (DQ) and a DQS adjustable delay line associated with the clock signal (DQS) based on the indicator signal to synchronize the data signal (DQ) and the clock signal (DQS).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.