DSI3 bus with enhanced robustness
US12052100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2022 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Apr 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0093
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and devices provide for enhanced robustness via graceful packet error detection and packet retransmission. One illustrative sensing method includes: generating a voltage pulse on a signal conductor coupled to a sensor array including one or more active sensors, the voltage pulse representing a broadcast read command (BRC) that defines a frame of one or more time-division-multiple-access (TDMA) slots, one slot for each active sensor to send a data packet; performing current sensing on the signal conductor to receive the data packet from each of the one or more active sensors; determining whether each said data packet is received error free; and requesting retransmission of each said data packet not received error free.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.