Ladder annealing process for increasing polysilicon grain size in semiconductor device
US12052868B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 18, 2021 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Jun 17, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67098
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor fabrication methods and semiconductor devices are disclosed. According to some aspects, a memory device includes a memory stack having interleaved a plurality of conductive layers and a plurality of insulating layers on a substrate, and a channel structure extending vertically in the memory stack. The channel structure includes a semiconductor channel extending vertically in the memory stack and conductively connected to a source structure. The semiconductor channel includes polysilicon, and a grain size of the polysilicon ranges from 100 nm to 600 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.