Three-dimensional memory and fabrication method thereof
US12052871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2021 |
| Grant date | Jul 30, 2024 |
| Priority date | — |
| Expiry date | Dec 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the method for forming the 3D memory device includes forming an alternating dielectric stack on a substrate, and forming channel holes that penetrate the alternating dielectric stack and expose at least a portion of the substrate. The method further includes forming top select gate openings that penetrate vertically an upper portion of the alternating dielectric stack and extend laterally. The method also includes forming slit openings parallel to the top select gate openings, wherein the slit openings penetrate vertically the alternating dielectric stack. The method also includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers, forming top select gate cuts in the top select gate openings, and forming slit structures in the slit openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.