3D stacked die testing structure
US12055586B1 · kind B1 · utility
0Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Feb 24, 2023 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Apr 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06596
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.