Memory devices and methods having multiple acknowledgements in response to a same instruction
US12056068B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jul 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device A memory device can include a serial interface (IF) configured to receive an operational code (op code) of no less than 16-bits and provide a plurality of acknowledgement values in response to the received op code. Controller circuits can generate the plurality of acknowledgement values, including first and second acknowledgement values in response to an operation indicated by the op code being completed, and first and third acknowledgement values in response to an operation indicated by the op code not being completed. Memory circuits can be configured to execute the operation indicated by the op code to access the nonvolatile memory cells, and indicate to the controller circuits whether or not the operation was completed. The first, second and third acknowledgement values can be different multi-bit values. Corresponding methods and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.