Multi-socket computing system employing a parallelized boot architecture with partially concurrent processor boot-up operations, and related methods
US12056497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jul 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-socket computing system employing a parallelized boot architecture with partially-concurrent processor boot-up operations. In a boot of the multi-socket computing system, a first, master CPU in a master CPU socket is configured to receive a master reset signal indicating a boot-up state. In response, the first, master CPU is configured to execute a first boot program code to perform a first CPU boot-up operation. To parallelize the boot operation of a second, slave CPU in a slave CPU socket, the execution of the first boot program code by the first, master CPU includes communicating a slave boot-up synchronization signal indicating the boot-up state to the second CPU to execute a second boot program code to perform a second CPU boot-up operation. The second CPU starts to perform its CPU boot-up operation partially concurrent with the performance of the CPU boot-up operation to reduce overall boot-up time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.