Method for forming chip structure with conductive structure
US12057419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Aug 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/13016
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a chip structure is provided. The method includes providing a semiconductor substrate, a first conductive line, and a first dielectric layer. The method includes forming a first conductive layer over the first dielectric layer. The method includes forming a second conductive layer over the first conductive layer. The method includes forming a second dielectric layer over the second conductive layer and the first conductive layer. The method includes forming a first through hole passing through the second dielectric layer, the first conductive layer, and the first dielectric layer. The method includes forming a first conductive structure in and over the first through hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.