Semiconductor package
US12057435B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2022 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jan 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/182
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.