Charge balance semiconductor device, in particular for high efficiency RF applications, and manufacturing process thereof
US12057474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2021 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Dec 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.