Integrated circuit including a capacitive element and corresponding manufacturing method
US12057513B2 · kind B2 · utility
0Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2023 |
| Grant date | Aug 6, 2024 |
| Priority date | — |
| Expiry date | Jun 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/42
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.