Device interface board compliance testing using impedance response profiling
US12061231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2020 |
| Grant date | Aug 13, 2024 |
| Priority date | — |
| Expiry date | Jan 31, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0091
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for compliance testing of a Digital Interface Board attached to Automatic Test Equipment in the testing of integrated circuit semiconductor devices using Impedance Response Profiling. The includes launching alternating voltage digital clock signals from the Pin Electronics to one or more circuit paths in the Digital Interface Board, and sampling a mix of the launched alternating voltage digital clock signals and reflected signals. The method also includes compositing time domain waveforms originating at the Pin Electronics, and generating an initial reflection response profile baseline. The method is repeated at a later predetermined time, generating a later reflection response profile. The method further includes comparing the initial reflection response profile baseline with the later reflection response profile, and determining whether the one or more circuit paths of the Digital Interface Board are in compliance with predetermined operating standards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.